DEVS-Suite

Sourceforge Community Choice Award Winner (March 2022).
Latest release: v7.0.0, January 2023.

Release Notes and Version History  Source Code (Sourceforge)

General-Purpose

Version 8.0.0

Details with documentation on the specific features of the latest and prior releases are provided here.

DEVS-Suite supports> Parallel DEVS, Cellular Automata (CA), Composable Cellular Automata (CCA) modeling and simulation> synchronized execution & animation> run-time linear/superdense I/O & state trajectories tracking and plotting> Action Level Real-Time (ALRT) modeling & simulation> model checking> Agent-Based Modeling (ABM)>CA & CCA playback> Knowledge Interchange Broker (KIB) interaction modeling > hierarchical model libraries > Black-Box testing & debugging > PostgreSQL repository>FMU co-simulation (OpenModelica)> OSATE (Architecture Analysis & Design Language)> domain-specific model libraries (Network on Chip); Software/Hardware co-design, Service-Oriented Computing (SOA), CCA cancer biology enabled with KIB-based composition of ABM and ODE/PDE models, Dynamic Structure, MIPS32 processors, and computer networks for education) and>Apache NiFi–enabled MongoDB repository for persistent simulation data on local and cloud hosts, supporting querying and visualization of simulation linear and superdense time trajectories.

https://sourceforge.net/projects/devs-suitesim/

More: http://devs-suitesim.sourceforge.net/

Special-Purpose

  • Action-Level Real-Time (ALRT) DEVS: Extends the Parallel DEVS formalism with real-time Statecharts, supporting time-windowed action execution and an abstract simulation protocol for real-time execution under constrained computational resources. Implemented in DEVS-Suite.
  • Black-Box Testing: Atomic DEVS-based testing framework for DEVS-Suite, enabling scripted test scenarios with input injection, output validation, and synchronization to ensure semantic correctness.
  • Model Checking (Verification): FMI co-simulation support using JavaFMI, enabling interoperability between DEVS-Suite models and FMUs, including those created with OpenModelica.
  • DEVS-FMU Co-Simulation: A Functional Mock-up Interface (FMI) using JavaFMI is developed for co-simulating DEVS-Suite models with Functional Mock-up Units (FMUs). The DEVS and FMUs, such as those created with the OpenModelica simulator, can be co-simulated.
  • OSATE-DEVS-Suite: An integrated AADL–DEVS environment that combines OSATE with DEVS-Suite, providing DEVS Annex behavior modeling and automated code generation for DEVS-Suite simulations.
  • Apache NiFi–enabled MongoDB: This feature of the DEVS-Suite simulator supports persistent simulation data storage on local and remote hosts along with querying and visualization of simulation results as linear and superdense time trajectories.
  • Postgres Timeview: A standalone tool for visualizing simulation results stored in a PostgreSQL database. Users can select input, output, and state variables from one or more simulation scenarios across multiple models. Supports PostgreSQL versions 12–14.

Domain-Specific

  • Dynamic Structure SOA-Compliant DEVS (DSOAD): A set of generic model components for dynamic structure modeling is developed for the DEVS-Suite simulator. They are used to simulate the dynamic publishers and subscribers with the brokered communication.
  • MIPS32processor (Education & Research)[included in DEVS-Suite Simulator Version 4]: A family of single-cycle, multi-cycle, and pipeline processor models for the MIPS32 (microprocessor without interlocked pipeline stages) architecture are developed according to Register-Transfer Level (RTL) and the parallel Discrete Event System Specification (DEVS) modeling formalism. The pre-defined models support teaching and learning the fundamentals of computer architectures.
  • Network-on-Chip: A detailed model for Network-on-Chip (NoC) is developed using the parallel DEVS simulator. These Constraint-DEVS models can be verified. The simulator’s model-checker is used to verify a model of the NoC router component at different scales. The state-space size, number of state transitions, and execution time metrics, without and with fault, demonstrate the verification of constrained-DEVS models.
  • Semi-conductor Supply-Chain Systems: A comprehensive set of DEVS models for simulating at a realistic level of details are developed. These models were developed for Intel semiconductor manufacturing.
  • Service Oriented Computing: The generic publisher, subscriber, and broker model components are formulated and developed in the DEVS-Suite simulator. A module for Quality-of-Service (QoS) monitoring is developed for evaluating SOC systems subject to exogenous changes.
  • Simple Computer Networks (Education) [included in DEVS-Suite Simulator]: A variety of models ranging from simple to complex processors to multi-architecture processors are developed. They serve to teach and learn the fundamentals of modeling and simulation. These models provide the basis for modeling large, complex component-based, multi-agent hierarchical systems.
  • (Software/Hardware Co-Design): A set of generic DEVS-based components are formulated for simulating Service-Oriented Computing systems. Modeling and simulation of the software and hardware co-design of Service-Based Software Systems are developed for the DEVS-Suite simulator. SOC-DEVS
  • Voice Communication System: This is an exemplar model of a communication-intensive Voice Communication System with an encryption software system. This model is developed using the SOC-DEVS approach and supported with the DEVS-Suite simulator.

Point of Contact: Prof. Dr. Hessam S. Sarjoughian ([email protected])

All Rights Reserved; Arizona Board of Regents (https://www.azregents.edu/); GNU Library or Lesser General Public License version 3.0 (LPGLv3)