Sourceforge Community Choice Award Winner (March 2022).
Latest release: v7.0.0, January 2023.


Version 7.0.0

DEVS-Suite is a Parallel DEVS simulator with support for1) synchronized execution & animation, 2) run-time linear/superdense I/O & state trajectories, 3) Action Level Real-Time modeling & simulation, 4) model checking, 5) ABM, 6)CA & composable CA playback, 7) KIB interaction modeling, 8) hierarchical model libraries, 9) Black-Box testing & debugging, 10) PostgreSQL repository, 11) FMU (OpenModelica), 12)OSATE (AADL) with domain-specific models: NoC; SW/HW co-design, Service-Oriented Computing, cancer biology, Dynamic Structure, SOA DEVS, MIPS32 processors, and computer networks for education.

Details with documentation on the specific features of the latest and prior releases are provided here.


  • Action-Level Real-Time (ALRT) DEVS: It is introduced into the parallel DEVS formalism using time invariants real-time Statecharts and supported for the DEVS-Suite simulator. Actions are specified in terms of time-windows that are to be executed in real-time. An abstract simulator protocol is devised for executing the ALRT-DEVS models under constrained computational resources.
  • Black-Box Testing: A scripting test framework derived from atomic DEVS is developed for the DEVS-Suite simulator. Test scenarios can be defined to inject inputs and interpreting outputs. Synchronization threading is used to nest the test script code within the state transition functions to guarantee the semantics correctness of DEVS models.
  • Model Checking (Verification): A model checking verification capability based on constrained-DEVS modeling formalism is formulated and developed. This is achieved by adding constraints on the state size and the number of transitions in the atomic model. The DEVS-Suite simulator has a model-checker modular for verifying parallel DEVS models using the DEVS simulator protocol.
  • DEVS-FMU Co-Simulation: A Functional Mock-up Interface (FMI) using JavaFMI is developed for co-simulating DEVS-Suite models with Functional Mock-up Units (FMUs). The DEVS and FMUs, such as those created with the OpenModelica simulator, can be co-simulated.
  • OSATE-DEVS-Suite: A tool built based on an integrated framework for the AADL (Architecture Analysis and Design Language) and DEVS (Discrete Event System Specification) modeling approaches. This tool integrates OSATE, a realization of the AADL framework and DEVS-Suite, a realization of the Parallel DEVS formalism. The tool supports DEVS behavior modeling called DEVS Annex and an engine for generating code for the DEVS-Suite.
  • Postgres Timeview: A standalone tool for visualization of the simulation results stored in the Postgres database  Users select desired input, output, and state variables in the DEVS-Suite simulator. The database can have the simulation results for any number of simulation scenarios belonging to any number of models. Postgres versions 12, 13, and 14 are supported.


  • Dynamic Structure SOA-Compliant DEVS (DSOAD): A set of generic model components for dynamic structure modeling is developed for the DEVS-Suite simulator. They are used to simulate the dynamic publishers and subscribers with the brokered communication.
  • MIPS32processor (Education & Research)[included in DEVS-Suite Simulator Version 4]: A family of single-cycle, multi-cycle, and pipeline processor models for the MIPS32 (microprocessor without interlocked pipeline stages) architecture are developed according to Register-Transfer Level (RTL) and the parallel Discrete Event System Specification (DEVS) modeling formalism. The pre-defined models support teaching and learning the fundamentals of computer architectures.
  • Network-on-Chip: A detailed model for Network-on-Chip (NoC) is developed using the parallel DEVS simulator. These Constraint-DEVS models can be verified. The simulator’s model-checker is used to verify a model of the NoC router component at different scales. The state-space size, number of state transitions, and execution time metrics, without and with fault, demonstrate the verification of constrained-DEVS models.
  • Semi-conductor Supply-Chain Systems: A comprehensive set of DEVS models for simulating at a realistic level of details are developed. These models were developed for Intel semiconductor manufacturing.
  • Service Oriented Computing: The generic publisher, subscriber, and broker model components are formulated and developed in the DEVS-Suite simulator. A module for Quality-of-Service (QoS) monitoring is developed for evaluating SOC systems subject to exogenous changes.
  • Simple Computer Networks (Education) [included in DEVS-Suite Simulator]: A variety of models ranging from simple to complex processors to multi-architecture processors are developed. They serve to teach and learn the fundamentals of modeling and simulation. These models provide the basis for modeling large, complex component-based, multi-agent hierarchical systems.
  • (Software/Hardware Co-Design): A set of generic DEVS-based components are formulated for simulating Service-Oriented Computing systems. Modeling and simulation of the software and hardware co-design of Service-Based Software Systems are developed for the DEVS-Suite simulator. SOC-DEVS
  • Voice Communication System: This is an exemplar model of a communication-intensive Voice Communication System with an encryption software system. This model is developed using the SOC-DEVS approach and supported with the DEVS-Suite simulator.

Point of Contact: Prof. Dr. Hessam S. Sarjoughian ([email protected])

All Rights Reserved; Arizona Board of Regents (; GNU Library or Lesser General Public License version 3.0 (LPGLv3)